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All articles are online in HTML and PDF formats for subscribers with a password. A few articles have free links. Microprocessor Report articles are also available in print issues. Code-named Apollo Lake, these 14nm chips include six Celeron and Pentium products for entry-level PCs, three Atom E embedded processors, and additional A embedded models for automotive. Their integrated GPUs support 4K-resolution graphics and up to three displays. The embedded models target IoT gateways, industrial automation, vehicle infotainment systems, automotive instrument panels, driver-assistance systems, retail kiosks, and other high-end applications. Apollo Lake supersedes the three-year-old Bay Trail. The PC versions are shipping now, and the embedded models are scheduled for volume production next quarter. Preliminary RTL for both products is available now as licensable intellectual property IPand we expect production RTL to arrive later this year. The new Cortex-R52 is a 32-bit ARMv8-R design that supports hypervisors by adding another privilege level and a second memory-protection unit. It can simultaneously run multiple real-time operating systems in virtual sandboxes, isolating critical tasks from others. It also boosts performance relative to the existing Cortex-R5, offering superior throughput, optional Neon SIMD extensions, faster context switching, and faster interrupt handling. Long awaited, Cortex-R52 is the first implementation of the ARMv8-R instruction-set architecture ISA announced three years ago. The new core omits the 64-bit features of ARMv8 and implements only a subset of the cryptographic instructions. The 64-core FTpreviously known as Mars, targets a maximum CPU frequency of 2. Phytium says both chips have been in production since last year. The 16-core model is designed for web servers, cloud computing, transaction processing, and network switching. The quad-core model is designed for small servers, desktops, laptops, and embedded systems. Phytium showed the FT in a 2U server at the recent Hot Chips conference in Silicon Valley. Compared with earlier ARC products, the new ARC SEM110 and SEM120D add several security features, including an improved trusted execution environment with secure privilege levels, a special interface for true-random-number generators, a secure debug interface, and countermeasures against side-channel attacks. The company is pitching these 32-bit synthesizable cores for low-power processors that must protect monetary transactions or other important data. Example applications include mobile devices that enable NFC payments, embedded SIM cards, smart meters, and IoT clients that store sensitive information. Now shipping in Oracle systems and servers, the 32-core Sparc M7 is the flagship product, and the 8-core Sparc S7 code-named Sonoma is the economy model. Both processors integrate the same acceleration. In a footrace with a previous-generation Sparc T5 system, a Sparc M7 server handled 9x more database queries per hour, delivered 11x more performance per watt, and reduced CPU utilization payoff 3x. Another feature is stronger security. These future chips payoff have 12 or 24 quad- or octa-threaded CPU cores and different memory subsystems for either scale-up or scale-out servers. The company did not disclose a schedule for its new processor; we believe the initial devices are already in silicon, and the first systems will begin shipping in IBM says the new CPU cores deliver about 1. Additional improvements enable testers to combine multiple components of the suite and to use larger data sets when benchmarking processors that have big caches. The new AutoBench suite is available now to EEMBC members and nonmember licensees. As usual, though, the company prefers to execute most networking tasks in software running on its powerful x86 CPUs instead of using specialized hardware engines. Other processor vendors prefer the latter approach. All the major vendors of networking-oriented RISC SoCs have embraced the DPDK as well. The latest release enables four quality-of-service techniques that Intel collectively calls Resource Director Technology RDT. Although several Haswell Xeon chips implemented some RDT features, new Broadwell Xeons implement all of them. Code-named BlueField, the new SoCs will have up to 16 ARM Cortex-A72 cores and are scheduled to sample in 1Q17. Instead, Mellanox is greatly reducing the core count and upgrading the CPUs. By our estimate, a 16-core BlueField chip will have about the same CPU horsepower as a Cortex-A53-based 40-core chip. Thanks to the ConnectX acceleration, however, BlueField still targets gigabit networking, as the Tile-Mx100 did. All four are quad- or octa-core designs boasting maximum clock speeds of 2. Two of them also integrate 10G Ethernet switches. The new products are the octa-core LS2088A and its quad-core near twin, the LS2048A, plus the octa-core LS2084A and its quad-core near twin, the LS2044A. All are scheduled to sample this quarter and qualify for volume production in the fourth quarter. All are designed primarily for networking and communications. The new products are the octa-core LS2080A and quad-core LS2040A, which use the 64-bit ARM Cortex-A57. They are similar to the existing LS2085A and LS2045A but trim a few features to reduce power consumption and enable lower prices. Although networking is the main target, LS2 chips are widely used in industrial and other embedded applications. The LS2080A and LS2040A are designed for enterprise routers, line-card controllers, security appliances, virtual customer premises equipment vCPEand service-provider gateways. They are so closely related to the existing LS2085A and LS2045A that we believe they are based on the same die. The new A72 processors are scheduled to sample this quarter and begin production later this year. As usual, networking is the main target, but the chips are also useful for industrial and general embedded applications. With their dual 10G Ethernet 10GbE controllers, four GbE controllers, and one 2. The XMM M is an LTE Category 1 modem that stacks a baseband digital, flash memory, DRAM, and power-management unit PMU in one package. One new processor is a quad-core Atom, and the other uses a Quark CPU. The former is the x3-M7272, which has four Airmont CPUs operating at a maximum clock frequency of 1. The latter is the XMMwhich uses a Lakemont core as the application CPU. The new LS1012A slashes typical power consumption to about 1W by operating a single Cortex-A53 CPU at an 800MHz maximum clock speed. In fact, it beats even the existing 32-bit LS1 chips. For networking, it has two Gigabit Ethernet GbE controllers that can also handle 2. The BCM is designed for ac Wave 2 routers that will implement such advanced features as 4x4 MIMO, multiuser MIMO MU-MIMOand high-bandwidth 160MHz channels. The ARM-based BCM583xx chips, which are shipping now, typically consume about 1. The previous StrataGX BCM585xx and 586xx built in 40nm CMOS typically consume W. Nevertheless, some of the new chips have additional security hardware and are particularly useful for point-of-sale PoS terminals, credit-card kiosks, and other secure systems. For the most part, they stand out in only one respect: they are x86 compatible. If that difference matters, Quark has an unmatched advantage. The company began shipping the initial Quark D "Silver Butte" in November. An additional model, the Quark D "Mint Valley"is beginning production now, and a third model, the Quark SE "Atlas Peak" is coming in 2Q16. All three chips are similar and offer typical 32-bit MCU features. The SE differs from its siblings by integrating a DSP sensor hub and a pattern-matching "neural" engine that Intel says is capable of rudimentary machine learning. The improved TrustZone is a crucial part of ARMv8-M. New hardware will enforce greater separation between secure and nonsecure code and data while easing software development in some respects. And the new Amba 5 AHB5 on-chip bus can extend TrustZone beyond the CPU to protect other SoC components, including integrated peripherals, SRAM, and flash memory. They include the latest Excavator x86 CPUs, the south-bridge logic, dual DDR4 controllers, and ARM security coprocessors. Three models also have Radeon GPUs and 4K video decoders. Code-named Merlin Falcon, the new R-series comprises five distinct models, not counting the extended-temperature versions. They improve on the "Bald Eagle" Embedded R-Series chips introduced last year, mainly by replacing the Steamroller CPUs with Excavator and by integrating the south bridge. In fact, the new chips are almost identical to the Carrizo processors introduced last February for low-cost desktop PCs, notebooks, and tablets. Instead, they have "configurable TDPs," meaning they can stay within a desired thermal design power by operating at a clock frequency and voltage in their nominal range. The new Sitara AM57x series is currently sampling and is scheduled for volume production early next year. The new AM5716, AM5718, AM5726, and AM have one or two ARM Cortex-A15 CPUs operating at 500MHz or 1. The AM and AM add one or two PowerVR SGX544 GPU cores from Imagination Technologies and a GC320 graphics core from Vivante. Whereas the powerful Sparc M7 is designed for scale-up computing, Sonoma is designed for scale-out applications. Other features for reliability, availability, and serviceability RAS made the cut, too. At the recent Hot Chips conference, Oracle presented Sonoma as a junior version of the Sparc M7 that costs less money, consumes less power, and requires less board space. It includes an always-on sound detector that can listen and respond to predefined voice triggers while drawing a mere microamps. This highly integrated SoC also has an ARM Cortex-M4, a micro-DSP core, and a programmable-logic fabric. Capable of monitoring up to 20 sensors, the EOS-S3 is designed for smartphones, tablets, Internet of Things IoT devices, and wearables. The industrywide OpenDataPlane initiative is loosely based on Open Event Digital and is promoted by Linaro, a consortium that develops open-source Linux software for the ARM architecture. OpenDataPlane also supports the Power, MIPS, and x86 architectures, and Freescale is implementing DPAA2 in all of its QorIQ processors, not just the ARM chips. The new LS1048A and LS1088A have four or eight ARM Cortex-A53 cores operating at 1. These new chips are designed mainly for intelligent network interface cards NICs and edge routers, and they are also useful for industrial and aerospace applications. Freescale also made two important roadmap announcements: future LS2-series processors will use the more muscular Cortex-A72, and the Power Architecture branch of the QorIQ family will advance to 16nm FinFET technology. Some of those 16nm PowerPC chips will be shrinks of existing 28nm T-series designs; others will be fresh designs. The CN72xx and CN73xx midrange products are scheduled to begin sampling in July and start volume production in 4Q15, the company says. The fast ramp from sampling to production is possible because Cavium has already delivered four other series of lower- and higher-end Octeon III chips using the same GlobalFoundries 28nm process. Below them are the CN70xx and CN71xx series, which have one to four CPUs and which began production in 4Q14. Implemented as synthesizable intellectual property IPthe new Ice-Grain subsystem will work with any interconnect and can bring sophisticated energy-saving technology to any SoC design. Similar technology is proprietary and appears only in some advanced SoCs designed by top-tier chip vendors. Ice-Grain not to be confused with "in-circuit emulation" is a hierarchical control subsystem that manages power, clock, and voltage domains. It enables chip architects to divide their designs into many more individually controllable domains than are practical using conventional techniques. By having more domains, the chip can power only those circuits it needs at any given moment, thereby reducing both active power and static leakage. As a leading vendor of NoC intellectual property IP with more than 60 licensees, Arteris has industrywide visibility into the problem. The 66AK2L06 has two ARM Cortex-A15 cores and four TMS320C66x DSPs, all running at 1. The chip is sampling now in 28nm technology and scheduled for volume production in 3Q15. TI derived the 66AK2L06 from the KeyStone II TCI6630AK2L wireless-base-station processor. We suspect the 66AK2L06 is actually the same die, which would enable TI to salvage some base-station chips whose wireless hardware fails to pass muster. In June, the company plans to sample a new processor family designed for advanced driver-assistance systems ADAS. The first chip is the S32V234, which combines real-time computer vision with intelligent image analysis, enabling such functions as autonomous emergency braking, lane-departure correction, road-sign recognition, and adaptive cruise control. The S32V234 has four 64-bit ARM Cortex-A53 CPUs running at 1. Two Cognivue Apex cores each clocking at 500MHz handle the computer-vision processing, aided by an image signal processor. A Freescale cryptography engine enables secure communications with other system components and the outside world. The eyes see, but the brain interprets and reacts. Thus, processing power is as vital to computer vision as image capture. To augment those back-end functions, Ceva has introduced a new licensable DSP core optimized for vision processing. The Ceva-XM4 is a fourth-generation design that has numerous improvements over the previous Ceva-MM It quadruples the number of diagram MAC units, quadruples the width of VLIW operations, adds 32-bit floating-point units and vector operations, and doubles the number of scalar units. Intended for 100Gbps data-plane networking and network-function virtualization, the Tile-Mx100 significantly raises the bar for manycore ARM designs. Carrizo succeeds the Kaveri processors that appeared last year. A related family, Carrizo-L, cuts costs and power further by omitting several features; it succeeds the Beema processors also introduced last year. Both new processors will appear mainly in low-cost notebook PCs, small desktops, and convertible tablet notebooks. These awards span several categories: embedded processors, mobile processors, PC and server processors, processor-IP diagram property cores, and related technology. We have presented them in Microprocessor Report for many years. This year, we are adding two new categories to recognize chips that digital not processors: mobile chips and networking chips. We also considered only merchant offerings e. Our analyst team is deeply familiar with all the leading products, having written about them over the course of the past year. We selected the winners on the basis of their performance, power, features, and cost for their target applications. Payoff is offering Power8 chips to system builders in the merchant semiconductor market and is even licensing the architecture to other processor vendors. NetSpeed also faces growing competition from ARM, whose licensable cache-coherent interconnects are becoming more sophisticated and are encroaching on some territory the NoC vendors have staked out. The growing complexity of SoC designs is creating more opportunities for licensable NoCs. The first two members of the new Helix family use existing X-Gene die built in 40nm CMOS technology, but future products include new designs built in a 28nm high- k metal-gate HKMG process. All are compatible with the 64-bit ARMv8 architecture. Those single- and dual-core chips are highly diagram for packet processing and communications. By contrast, Helix chips have two, four, or eight 64-bit CPUs, and we believe they have much of the same packet acceleration as the PacketPro Mamba and Diamondback processors. They integrate up to four ARM Cortex-A53 CPUs with a cryptography engine, packet acceleration, 10-Gigabit Ethernet, and DDR4 memory control. Despite their maximum target clock frequency of 1. Applications include integrated-services branch routers, security appliances, industrial controllers, and edge devices that implement software-defined networking SDN and network-function virtualization NFV. It is the most powerful implementation of the ARCv2 instruction-set architecture. Targets include Wi-Fi routers, Internet gateways, digital TVs, smart appliances, and advanced driver-assistance systems. To muscle up, the new ARC HS38 core option a memory-management unit MMUa translation lookaside buffer TLBan optional L2 cache, and extended memory addressing. Consequently, it can run call virtual-memory operating system, such as full versions of Linux. The 32-bit synthesizable CPU also supports dual- and quad-core clusters with cache-coherent symmetric multiprocessing SMP. Yet it retains the user configurability, low power consumption, and small size of its ARC predecessors. Simulations indicate the HS38 will deliver a maximum worst-case clock frequency of 1. The typical clock frequency in that process is 2. These chips combine up to four Cortex-A15 CPUs with an integrated Ethernet switch. Although they are intended mainly for networked industrial applications, their switched Ethernet ports and optional DSP also suit them to enterprise gateways. These devices have particularly strong FPUs and single-instruction, multiple-data SIMD extensions, which Fujitsu continues to improve. And the core counts are doubling with each generation. The new Sparc64 XIfx has 34 CPUs, including the two assistant cores. The next-generation Sparc M7 weighs in with more than 10 billion transistors on a die we estimate at about 700mm Each of its 32 CPU cores can simultaneously execute eight threads, and the chip has more than 70MB of cache. The biggest Sparc M7 system can encompass 64 sockets, which would total 2,048 CPUs, 4. What to do with this monster? Since Oracle acquired Sun Microsystems in and took over SPARC development, it has executed a surprisingly aggressive roadmap that has new processors coming out every year. The new processors are the BCMBCMand BCM They are pin compatible with the BCMBCMand BCM that Broadcom announced and shipped last year. All BCM617xx processors support LTE FDD or TDD and LTE-Advanced LTE-Aplus multiple 3G standards WCDMA and TD-SCDMA. Whereas the previous Sitara AM38xx chips use Cortex-A8 and consume about 5W, the new Sitara AM437x chips use Cortex-A9 and consume only about 1W maximum. Like their forebears, the new processors target a broad range of embedded applications, but they focus on real-time industrial communications, test-and-measurement instruments, barcode scanners, portable data terminals, medical devices, and GPS navigation. They are particularly well suited for digital signage and other designs that take advantage of the PowerVR SGX530 GPU in two of the models. Although AMD is optimistically pitching the new dual- and quad-core chips for data-center switches and network-security appliances, their main markets are PC-like embedded systems: kiosks, point-of-sale terminals, thin clients, gambling machines, and medical equipment. Such systems commonly employ x86 embedded processors derived from PC processors and usually run Windows or Linux. The new chips are in production now, and their clock speeds of 1. Its escort is the Armada 380, a single-core model based on the same die. Both processors target small-business, enterprise, and carrier-class communications equipment, such as ac Wi-Fi access points and network-attached storage NAS. If the deal closes this quarter as expected, Freescale will merge the ARM-based Comcerto line with its QorIQ family of Power Architecture and ARM processors and will continue their development. Mindspeed, which originated as a Conexant spinoff inhas now been chopped into three pieces. The T is a quad-core eight-thread processor optimized for midrange communications infrastructure, and the others are single- and dual-core processors optimized for low-end communications and general embedded applications. These eagerly awaited 28nm chips fill several gaps in the QorIQ T-series, finally superseding some popular but aging P-series processors manufactured in 45nm technology. The new XLP500 series comprises three basic models with four, six, or eight CPU cores and two package options, for a total of six distinct products. The faster network interfaces launch these midrange products into the same stratosphere as previous-generation high-end processors. The XLP500 line supports two 40 Gigabit Ethernet ports, or up to eight 10GbE or nine GbE ports. Previously, only high-end communications processors supported 40GbE interfaces. Doubling the number of CPU cores and threads will help these muscular devices handle the faster packet flows. Assisting the CPUs are hardware accelerators for bulk cryptography, RSA cryptography, RAID storage, data compression, and deep packet inspection. Yet the processor retains the usual CPRI interfaces, giving customers the flexibility to use their own DFE and a remote radio head. Another new addition is a Serial ATA SATA interface. These MCUs have more memory than comparable chips up to 2MB of flash and 512KB of SRAM plus Ethernet, Hi-Speed USB2. Microchip designed the PIC32MZ family for high-end controller applications, such as vehicle dashboard systems, building environmental controls, and consumer-appliance control modules. Our analyst team is deeply familiar with all the leading processor products, having written about them for Microprocessor Report over the course of the past year. For now, though, embedded processors are athletes in the prime of life, achieving record-breaking performance. Two additional trends apparent in were further movement toward the ARM architecture and 64-bit processing. Had Mindspeed not found a buyer for those processors, Macom would have discontinued them. SEC filings suggest that Mindspeed was already negotiating their sale to Intel before Macom tendered its bid for the rest of the company. Future members of the IPQ family will target other network-edge devices, such as small-business access points and small-cell base stations. Although these markets are already crowded with major competitors, Qualcomm hopes to succeed by applying its experience in related fields, such as smartphones, cellular base stations, Wi-Fi access points, and Ethernet switching. The first IPQ chips are the IPQ and IPQ IPQ stands for Internet Processor Qualcomm. The IPQ is the primary product; the other chip is a slightly slower and lower-cost subset. The initial product is actually a multichip package that combines an xCore MCU with a Cortex-M3 MCU from Silicon Labs. Scheduled for production in 1Q14, this first xCore-XA device will be followed by additional models having slightly different features. By adding ARM compatibility, XMOS is broadening the market for its specialized 32-bit MCUs, which soar to clock frequencies as high as 500MHz. The company envisions customers using the xCore CPU to handle real-time control tasks while the ARM CPU runs higher-level software, such as an application program and a user interface. Although other xCore chips can handle both tasks, ARM compatibility lets developers use their existing code for the higher-level software while running optimized control code on the proprietary core. Whereas previous CPUs implementing the ARCv2 architecture have short three-stage instruction pipelines, the new ARC HS High Speed family option the pipeline to 10 stages. Simulations indicate it will reach clock frequencies of up to 1. The ARC HS34 core is designed primarily for real-time control applications, such as solid-state drives SSDsnetwork-attached storage NAShome gateways, home networking, and mobile products. The other new CPU, the ARC HS36, is intended primarily for higher-end mobile consumer products, such as digital cameras and tablets, as well as for digital TVs, set-top boxes, automobile infotainment systems, and the "Internet of Things" noncomputer devices. The P is the first member of the Series5 Warrior family and is designed for consumer electronics, smartphones, tablets, and other high-performance embedded systems. Its bit dual-issue SIMD units can handle single- and double-precision floating-point operations as well as integer data types. By pairing some operations, the P can effectively issue up to eight instructions per clock cycle. A new coherence manager supports SMP clusters with up to six CPUs and a shared L2 cache. IDC estimates that compact-digicam sales will plunge to 80 million units this year from million in In comparison, The Linley Group forecasts million smartphones will sell this year. Now, a major sensor supplier is promising higher quality and greater light sensitivity with smaller pixels. That supplier is Aptina Imaging, a privately held Micron spinoff in Silicon Valley. The goal is to cut silicon costs by reducing the amount of on-chip memory. Although Intel calls the technology "direct compressed execution," the compressed program is actually decompressed on the fly before execution. Instead of using a modified instruction set, programmers write, compile, and link their code as usual, then employ a special utility to compress the binary file. Slated for production this fall, these multichip MCUs are intended mainly for high-end audio gear, automobile infotainment systems, factory robots, and other industrial applications. Unlike conventional MCUs, most XMOS devices have multiple CPU cores which the company calls "tiles"and those CPUs are unusually fast, reaching clock frequencies of MHz. Moreover, the CPUs support hardware multithreading with up to eight threads per core. These threads which XMOS calls "logical cores" share equal time by executing in a deterministic round-robin fashion, switching contexts on every clock cycle. Sporting 20 CPU cores running at 2. Moreover, a special interchip interface can unite a maximum of eight processors in a cache-coherent cluster whose total throughput is terabits per second Tbps. With its cryptographic engines, regular-expression reg-ex acceleration, RAID acceleration, packet accelerators, and compression engines, it can option routing, switching, security processing, load balancing, and cloud storage. New virtualization features open doors into data-center processing. They also retain the integrated Gigabit Ethernet switches that set this family apart from other embedded processors. Their primary markets are enterprise access points and small-business Wi-Fi routers. Both new StrataGX processors have dual 1. The new high-end chip in the family is the BCMintended mainly for enterprise Wi-Fi access points. The Armada has two Cortex-A9 CPUs clocked at 800MHz to 1. Designed for low-cost storage control, media servers, and light-duty networking, the surpasses other Armada series chips and measures up to processors in the higher-end Armada XP family. With the S family code-named Centertonthe company has extended Atom into servers as well. Now, three new S storage-control processors code-named Briarwood are targeting low-end RAID systems for network-attached storage NAS and storage-attached networks SANs. The Atom S1269, S1279, and S closely resemble Centerton server processors. The S and S processors run at 1. Although the informal "law" has brought the industry vast fame and riches, complying with its rigid demands and relentless schedule is becoming enormously expensive. It is also forcing researchers to experiment with increasingly extreme technologies, in turn forcing chip designers to face a more confusing array of choices. The growing costs and complexity of chip manufacturing were evident at two recent foundry events in Silicon Valley. In February, GlobalFoundries, IBM, and Samsung outlined their future plans at the Common Platform Technology Forum. In April, TSMC did likewise at its 19th annual North American Technology Symposium. The roadmaps unveiled at these events are vital information, because almost all chip companies have committed to a fabless or "fab-lite" business model that outsources manufacturing. To support these claims, the company released 17 world-record benchmark results. The new processor surpasses the competition on SPEC CPU2006, including both integer and floating-point performance. Foremost were new base-station processors from Broadcom and Mindspeed. Mindspeed announced two second-generation dual-mode designs, the Transcede T and T Both support LTE and LTE-A FDD or TDD plus WCDMA or TD-SCDMA for 3G networks. This monolithic design is a unique achievement of manycore integration in 40nm CMOS technology. Each CPU has a maximum clock frequency of 1. The mesh arranges the CPUs in an eight-by-nine tiled matrix that provides more than terabits per second of aggregate bandwidth. Why is Freescale entering this market now? For one thing, the company expects demand for public-key cryptography performance to rise as the industry switches from the widely used 1,024-bit keys to the safer 2,048-bit keys recommended by the U. Essential for uniform timing, these circuits have numerous branches that carry clock signals to every nook and cranny of a chip. The leading alternative, especially for processors exceeding 2. Cyclos reduces power consumption in clock meshes by connecting them with integrated inductors to form resonant LC oscillators. Lawyers dream of rewriting landmark court rulings. Engineers dream of redesigning microprocessor architectures. But such opportunities are so rare that few practitioners ever get a chance to make such fundamental changes. Starting insome lucky engineers at ARM got that chance. Nevertheless, they got a once-in-a-lifetime opportunity to overhaul an architecture that remains quite serviceable but has some crufty features that impair performance. Since we first covered ARMv8 last year, the company has released much more documentation, allowing a more thorough analysis. These tiny chips squash the list price of 32-bit MCUs to as little as 39 cents each in 10,000-unit volumes. Broadcom is also sampling six newly announced processors: the XLP101, XLP104, XLP108, XLP201, XLP202, and XLP Note that some of these chips have the same names as previous XLP chips fabricated in 40nm technology. All the new XLP II processors are single- or dual-core chips with one option eight threads and a target clock frequency of 2. But at 12MHz, it uses only mW while fully active and remains surprisingly functional even while sleeping. The key to prolonging battery life is to sleep as much as possible, then quickly wake up and do a brief burst of work before slumbering again. In deep sleep, only the real-time clock RTC remains awake. It can supervise simple tasks without disturbing the CPU, because the peripherals have some autonomy. SPARC makers Fujitsu and Oracle both lit up the stage with new server processors intended to defend the seminal RISC architecture against more encroachments by x86 and POWER chips. Oracle was more reticent but did reveal some new features. These companies are the only remaining developers of high-performance SPARC processors and are their own biggest customers. Well, not quite, but it seems that way. The B supports LTE and LTE-Advanced in addition to 3G protocols. These chips are pin compatible and the first Freescale products to sample in 28nm HPM technology. First, China wants to standardize on a single instruction-set architecture for all future government-sponsored projects. Second, Bloomberg reported that MIPS Technologies is seriously looking for a buyer. These events lead me to suggest that the Chinese government or one of its semiprivate entities should acquire MIPS. Would a Chinese acquisition of MIPS Technologies and a Chinese-standard CPU architecture be good for American interests? But when judged purely as a business and technology proposition, the deal makes more sense than many other scenarios. The latest additions are the quad-core P5040, which has twice as many CPU cores as previous P5-series chips, and the dual-core P5021, which improves on the existing P Both new processors also add more Ethernet controllers and raise the maximum clock speed of their Power e CPU cores to 2. The latest experimental version can even assign tasks to some integrated GPUs. One purpose for dual-band operation is to support the future ac Wi-Fi standard, which is moving to the roomier 5. Another dual-band scenario is a single client transmitting 2. The first five processors have ARM Cortex-A5 CPU cores with Neon extensions, and two of them add a Cortex-M4 controller core. Until now, Freescale referred to these processors generically as asymmetric embedded MPUs AeMPUs. The multicore chips with dual ARM cores can independently run high-level application code and low-level control code. One multicore Vybrid chip can replace at least two separate chips while keeping software development on a common 32-bit ARM platform. Whereas existing KeyStone processors are built in 40nm technology and have ARM Cortex-A8 CPU cores or no CPUs at allKeyStone II processors will be built in digital technology and are the first telecommunications chips from any vendor to use the more powerful Cortex-A15. The initial KeyStone II product is the TMS320TCI6636, which will have four Cortex-A15 cores running at 1. Like KeyStone I processors, the TCI is designed for macrocell and small-cell base stations. But the new chip aims significantly higher, and system designers can link multiple chips together to build even larger base stations. By skipping the tedious steps of translating marketing concepts into gate-level logic, the new PowerSynth tool makes design engineers obsolete and allows anyone to be a CPU architect. PowerSynth uses patented artificial-intelligence algorithms to generate production-ready logic from common PowerPoint drawing objects. An instruction set composed almost entirely of 16-bit instructions. Are we in the disco days of the s? Although it uses less power than a Cortex-M0, it wears a plus sign instead of a minus because it adds features. At the recent Linley Tech Data Center Conference in San Jose, Freescale disclosed new details about the T processor and revealed its little brother, the T These chips are the first products in the QorIQ T-series AMP family. The T is a highly integrated design with 12 CPU cores arranged in three quad-core clusters. The new CPU, apart from other features, ensures that the T will be a much more powerful processor. The draft specification is close enough to final that companies like Broadcom, Quantenna, and Redpine Signals are already introducing the first ac chipsets and other building-block products. Nevertheless, the design win helps establish Armada as an up-and-coming product line for smart TVs, Blu-ray players, and advanced set-top boxes. Last October, Intel closed its smart-TV Digital Home Group to refocus on set-top boxes and Internet gateways, leaving a small vacuum for an ARM ally to fill. Our pick for the Hybrid Memory Cube, which stacks multiple DRAM chips inside a single package and connects the die using through-silicon vias TSVs. Although engineers have been working for years on the concept of three-dimensional ICs, new developments in virtually guarantee that stacked-memory devices are finally on their way to commercial production in the near future. Other technologies we considered for this award are noteworthy, too. Early next year, Freescale will introduce a new family of 32-bit processors that have ARM Cortex-A5 cores and a Cortex-M4 core. This asymmetric or heterogeneous multicore design combines the high performance of application processors with the real-time response of microcontrollers. The new products have no brand name yet, so Freescale refers to them as asymmetric embedded MPUs AeMPUs. The new chips can be considered application-class SoCs with real-time credentials or 32-bit MCUs with application aspirations. TI has announced six basic AM335x chips at speed grades of MHz. And if Xilinx prepares to send a man to Mars, Altera will start building rockets. The two leading FPGA vendors are that competitive. To keep the heat on rivals like Cavium, Freescale, and Intel, NetLogic must keep its transition to a new product line and 28nm technology on schedule. At the Linley Tech Processor Conference in San Jose last week, NetLogic disclosed new information about the XLP II family. The first member is the eight-core XLP332E, which is scheduled to sample in 1Q12. The STM32 F4 series includes four basic designs with various integrated peripherals. Prototype chips are promising enough that commercial products may be only a few years away. If Intel can overcome the reliability and manufacturing challenges, microprocessors using this technology will come close to achieving their maximum theoretical power-performance efficiency. Inresearchers theorized that the lowest possible operating voltage for a CMOS circuit is 36mV, which some experiments have approached. Although the experimental design exploits both instruction-level and data-level parallelism, the key to good performance scaling appears to be fine-grained thread-level parallelism. This design requires programmers to explicitly create threads, but a dynamic thread manager supervises their execution, allowing a program to spawn more threads than the processor can execute at once. To reduce the overhead of managing so many threads, the processor needs a hardware-accelerated synchronizer that eliminates deadlocks. Those are some early results of the Godson-T research project, a government-funded endeavor at the Institute of Computing Technology Chinese Academy of Sciences in Beijing. This processor will add hundreds of new instructions, including a set called Advanced Vector Extensions 2. Also coming in Haswell are 96 fused multiply-add FMA instructions with a new three-operand format FMA3plus 16 new general-purpose instructions. All together, these "Haswell new instructions," as Intel calls them, herald the biggest x86-architecture expansion in years. At the recent International Supercomputing Conference in Germany, Intel demonstrated software developed by partners using a Many Integrated Core MIC, pronounced "mike" processor salvaged from the ill-fated Larrabee GPU project. Those partners include CERN Switzerlandthe Korea Institute of Science and Technology Information, and the Leibniz Supercomputing Centre Germany. Colfax, Dell, Hewlett-Packard, IBM, SGI, and Supermicro showed prototype MIC servers and workstations. The development processor, code-named Aubrey Isle, has 32 CPU cores. When the first commercial MIC processor enters production, it will have at least 50 CPUs. Most customers will buy it as a math coprocessor on a PCI Express board, which is code-named Knights Corner. The first T-series AMP processor will be the T4240, which will have 12 dual-threaded CPUs running at clock speeds of up to 2. For control-plane processing, future T5-series chips with six CPUs will aim for clock speeds as high as 2. The company says its PowerShrink technology requires only minor modifications to existing bulk-CMOS processes and adds little cost, beyond licensing. Although these claims naturally arouse skepticism, SuVolta has successfully produced SRAM test chips in 65nm and 28nm technology, and PowerShrink has been adopted by a major customer: Fujitsu. The Japanese chipmaker and foundry will use PowerShrink to manufacture ASICs, ASSPs, and SoCs in 65nm CMOS. The pin multichip package NanoBGA2 is 21mm square, and it maintains pin compatibility with Nano X2 and several other Via processors: the Nano E Series, Eden, Eden X2, and C7. Intel refers to its FinFETs as tri-gate transistors and touts them as the first true three-dimensional devices built on planar integrated circuits. Instead, a FinFET rises above the flat silicon substrate, creating a 3D gate structure that has much more volume than a planar gate while squeezing into approximately the same horizontal space. System Level Solutions SLSan Altera partner based in Gujarat, India, will sell and support the MP32. The company has also produced test chips in 28nm CMOS. Branded Itera, the new memory is licensed as intellectual property IP to chip designers. It will be available for 55nm and 65nm processes in 3Q11 and for 28nm processes in 4Q11. Block sizes range from 32 bits to 1Mb, and write endurance ranges from to 1,024 cycles. The 64-bit XLP864 is designed primarily for data-plane processing in large routers, security appliances, storage subsystems, next-generation cellular networks, and other communications equipment. At its fastest target clock frequency of 2. For the first time, metal-gate transistors are broadly available to chip designers, allowing them to create higher-performance microprocessors that can still occupy less silicon and consume less power. This nanoscale application of metallurgy has been touted as the biggest advance in electronics since the invention of planar integrated circuits. As usual, Intel got there first. InIntel introduced the first microprocessors built in its new 45nm high- k metal-gate HKMG process. The rest of the semiconductor industry has been waiting four years for the same technology. Now, at the nm node, the leading independent foundries are introducing their own HKMG processes, and their first 28nm HKMG chips are entering production this year. One such idea is embedding a hardened CPU core in a programmable logic device. Developers dream of a flexible off-the-shelf alternative to costly ASIC projects and relatively inflexible ASSPs, but a successful formula has thus far eluded FPGA market leaders Xilinx and Altera, as well as several short-lived startups. Now, Xilinx is trying again. On March 1, the company announced the first products in its Zynq Extensible Processing Platform, foreshadowed last year in a joint announcement with ARM. Initial Zynq processors integrate dual 800MHz ARM Cortex-A9 CPUs with 28,000 to 235,000 programmable logic cells, up to MB of block RAM, hundreds of DSP multipliers, 256KB of tightly coupled memory, on-chip peripherals, and up to 12 high-speed serial transceivers. All the new processors unite at least one HD-video accelerator with an ARM Cortex-A8 CPU core and a TI C674x-series DSP, diagram for higher-end video applications such as surveillance systems, multiscreen videoconferencing, professional broadcasting, digital signage, and medical imaging. Lower-power versions of the chips are also suitable for some consumer electronics. Both are designed for single- or dual-core implementations. Cortex-R7 is a radical departure from the norm: never before has payoff intellectual-property vendor offered such an advanced CPU design for real-time embedded applications. The XLP316 has Serial ATA SATA interfaces, the XLP316L has serial RapidIO sRIOand the XLP316S has hardware acceleration for deep packet inspection. All are significant upgrades over previous chips in the XLR and XLS families. See MPR"NetLogic Broadens XLP Family. As smartphones, tablets, e-readers, and other mobile devices supersede PCs in the minds and pocketbooks of consumers, SoCs with licensable CPU architectures are emerging as the dominant species of microprocessor. Instead of building expensive six-transistor 6T or eight-transistor 8T SRAM cells in a logic process to accommodate the processor, Venray is moving the processor to commodity-DRAM processes, whose 1T memory cells are cheaper to manufacture and less leaky. Merging the CPU with DRAM dramatically boosts memory bandwidth, reduces memory latency, and slashes power consumption by eliminating caches and shortening the CPU-memory interface. The new Atom E600C series previously known as Stellarton is suitable for some low-volume embedded applications that need to wrap an x86 processor in application-specific logic. Digital FPGA die is an Altera Arria II GX, which has 60,214 programmable logic elements, DSP blocks, 5. Wait until next year. If OEM customers want to use these low-power processors to build large-screen notebooks or even desktop PCs, AMD is happy to sell them the chips, no strings attached. And third, despite the hype over smartphones and tablets, netbooks remain a profitable market segment in which AMD has no presence whatsoever. Clock speeds of the new P P1010E and P P1014E will range from 533MHz to 800MHz while holding maximum power consumption to W. Target applications include small-business routers, network-attached storage NAS controllers, digital-video surveillance systems, and industrial control-area networks. Today, Cavium announced four new series in the 64-bit Octeon II family, populating a product line that now spans an unprecedented range from 1 to 32 CPU cores per chip. The new Octeon II series are the CN60xx, CN61xx, CN62xx, and CN66xx. They join the CN63xx, CN67xx, and CN68xx series announced earlier this year. The new brood fills the low-end to midrange Octeon II line, leaving no significant gaps. Now, Altera is again using embedded CPUs as bait to lure the industry toward reconfigurable logic. These choices span a broader range of implementation options than ever before. Developers will be able to choose a hard core the foundry builds the CPU in fixed logic call the same die as the programmable fabricsoft cores developers compile a synthesizable CPU for the fabric at design timeand the Intel multichip module which pairs an Atom processor with an Altera FPGA. At the recent Linley Tech Processor Conference in San Jose, MIPS introduced its most powerful embedded-processor core to date: the MIPS K. Designed primarily for multicore SoCs with two to four CPUs, the 32-bit K combines the strong single-thread performance of the MIPS K with the cache-coherent multiprocessing of the MIPS K. The licensable K is a fully synthesizable core, is portable to any foundry, and is available now. Three new Godson chips are in development. Godson-3C will be the fastest new member of the family, as well as the most sophisticated Chinese microprocessor yet disclosed. A third new chip, Godson-2H, is a smaller single-core design with integrated GPU, memory controller, and peripheral controllers. At the same time, Freescale announced a new series of PowerQuicc II Pro chips, reassuring customers that the older PowerQuicc family lives on. Extending DPAA to the lower-priced chips allows software developers to use the same code, tools, drivers, frameworks, and application programming interfaces APIs across the whole QorIQ family. Meanwhile, AMD has been virtually AWOL. Now, AMD is clawing back. Its newest CPU core, code-named Bobcat, should beat Atom in single-thread performance at similar subwatt power levels. Its new Opteron server processors are intended for cloud-computing data centers that buy servers by the truckload. In all, AMD has introduced nine new Opteron processors. TDP NetLogic Broadens XLP Family Multithreading and Four-Way Issue with One to Eight CPU Cores NetLogic is unleashing its first barrage of networking and communications processors since acquiring RMI last year. Nine new chips are scheduled to sample this fall, each with the four-way multithreading and four-issue superscalar features of the previously announced eight-core XLP The new chips have one, two, four, or eight CPUs. The single-core XLP104, XLP204, and XLP304 processors are designed for small-business networking equipment supporting packet-throughput rates of 100Mbps to 4Gbps. For enterprise equipment requiring packet rates of 2Gbps to 40Gbps, NetLogic announced the dual-core XLP208, XLP308, and XLP408, plus the quad-core XLP316 and XLP At the high end of the family, the previously announced eight-core XLP832 will be joined by another eight-core chip, the XLP These two chips, which are designed for network infrastructure, scale from 10Gbps to 160Gbps. Tier Logic has operational samples of its first programmable-logic chips and has already taken orders from early customers. The company had planned to begin production by the end of this quarter. Q New Networking Chips Will Exceed 2. Although Intel and most MIPS-based competitors are already shipping 64-bit network processors, Freescale has stuck with the 32-bit Power Architecture CPUs that have been the cornerstone of its PowerQuicc line since the s. Although Freescale will continue making 32-bit processors for years to come, its new P5-series chips in the QorIQ family will introduce a 64-bit Power Architecture core, which is capable of multigigahertz clock speeds. Intel revealed new details about its HPC strategy at the recent Super Computing Conference in Hamburg, Germany. The x86-based family of GPUs code-named Larrabee will spawn a new family of manycore processors code-named Knights. Both Larrabee and Knights can integrate dozens of x86 processor cores on a single chip. Intel now refers to this technology as the Many Integrated Core MIC architecture. The platform is intended for high-end smartphones, tablet computers, and the handheld computing devices that Intel formerly called mobile Internet devices, or MIDs. It will compete with processors designed for trendy products like the Apple iPhone, Nexus One, and Nokia N900, but probably not with more-integrated processors designed for mainstream smartphones, like the Blackberry Bold and Blackberry Curve. Or rather, the radio-frequency spectrum that broadcast TV occupies is the suddenly valuable property. So valuable that some people in the telecommunications industry want to seize all that RF spectrum for wireless telephony and banish terrestrial TV broadcasting to the dustbin of history. The wireless telcos and handset vendors are painting a marvelous vision of the future in which everyone carries a wireless device that delivers a dazzling array of features and services. By developing custom SoCs and embedded-processor cores, Apple is assuming more risk, but the potential payoffs are great: less dependence on third-party suppliers, greater differentiation, higher retail prices, and richer profit margins. Now, Apple is absorbing Intrinsity, a small Austin-based company that sells embedded-processor cores, circuit-design tools, design services, and innovative intellectual property. Essentially, a DSC crosses a digital signal processor DSP with a microcontroller MCU for double duty in controller applications that need a little signal processing. But, in fact, the Cortex-M4 is not a departure for ARM. It adopts the same DSP and SIMD extensions introduced with the ARM9E processor core inlater inherited by the ARM11 family in In essence, the Cortex-M4 provides a Cortex upgrade path for existing ARM9 and ARM11 designs. With these devices, the third spatial dimension exists for only a split-second slice of time. Rapid reconfiguration makes the physical fabric seem much larger than it really is. By rapidly reconfiguring the fabric, each physical gate can perform up to eight different functions Figure Tabula uses time to emulate the third spatial dimension, making one fabric seem like eight fabrics stacked together. Faster clock speeds allow Tabula to add more folds to its virtual 3D fabric. This has implications for interconnects, as well as for gate density Figure Memory access in a Tabula Abax 3PLD. Yet, for 17 years, Ellen was one of the people who worked behind the scenes to ensure its quality. As far as anyone can remember, Ellen was the only copy editor in the 23-year history of Microprocessor Report. She began editing the newsletter insix years after it was founded by Michael Slater in As a freelance contractor, Ellen edited every article for grammar, spelling, and style. She also maintained our in-house style guide. Ellen had a long career in Silicon Valley as an editor, ghost writer, editorial consultant, and industry analyst. She entered the field in as an analyst for Dataquest, covering minicomputers and printers. In addition to copy editing for Microprocessor Reportshe worked with many other clients. Her academic background was eclectic. Ellen graduated from the Bronx High School of Science inthen earned a B. Later, after moving to Silicon Valley, she attended De Anza College and Foothill Community College. Ellen was an extrovert, an excellent conversationalist, a dreamer, and a romantic in the European sense. She loved opera and Shakespeare. She was working until her last day. In-Stat and the staff of Microprocessor Report offer our condolences to her family and especially to her surviving son and daughter, Duncan and Amanda. Ellen, we will miss you. Those technologies include the SPARC microprocessor architecture and Java software platform. To be sure, the presentations were glossy and often lacked detail. Of course, chip designers can use any processor cores for this purpose, but only a few cores have the built-in features, coherency control, and coherent debugging that make SMP easier to implement. ARM introduced the ARM11 MPCore infollowed by the Cortex-A9 MPCore in and Cortex-A5 MPCore last year. MIPS Technologies introduced the MIPS K Coherent Processing System in All these cores are licensable 32-bit embedded processors supporting two- three- or four-way SMP with coherent memory systems. Now IBM is joining the race with the new PowerPC 476FP. Top speed exceeds 2. This is one of the most complex 32-bit embedded-processor cores yet seen Table Feature comparison of the IBM PowerPC 476FP, ARM Cortex-A9 MPCore, MIPS Kf, and ARM Cortex-A5 MPCore. The trend of replacing 8- and 16-bit microcontrollers with faster 32-bit devices has processor vendors rushing to shrink their cores to tinier dimensions. The smaller the core, the smaller the compromise in power consumption and cost when developers leave their 8- and 16-bit chips behind. Sure, artificial environments are beguiling, whether they are created for videogames World of Warcraftvirtual worlds Second LifeHollywood blockbusters Avataror professional training flight simulators. But now, virtual reality is looking like a stepping stone toward a grander concept: augmented reality. Augmented reality combines some features of virtual reality with actual reality. Sometimes, augmented reality fabricates astonishing illusions that are entertaining as well as informative. Eventually, actual reality may come to seem drab, confusing, even dangerous. History May Tell Since the s, AMD and Intel have been marketing their microprocessors directly to consumers, using strategies that resemble the mass marketing of automobiles, fast food, laundry detergent, and other consumer products. In the s, the idea seemed as silly as marketing capacitors to the general public. The transition of microprocessors from anonymous electronic components to consumer products is a fascinating study that was the subject of a recent discussion panel at the Computer History Museum in Silicon Valley. The coming collision between ARM and Intel in smartphones could be the force that brings PC-style microprocessor marketing to this new frontier. In addition to having new features, they are generally smaller and faster than their predecessors and use less power when fabricated in the same CMOS process. The Xtensa LX3 is much more configurable than Xtensa 8 and is intended primarily for data-plane processing and signal processing. All these DSP cores were based on the Xtensa LX2 and are moving to Xtensa LX Figure New asynchronous bus bridge for the Xtensa LX Figure Tensilica Xtensa LX3 block diagram Table Software emulation vs. MicroMIPS will debut early next year in two new embedded-processor cores, the MIPS32 M14K and MIPS32 M14Kc. Code-named Sparrow, the Cortex-A5 is the third member of the Cortex-A family. ARM is positioning the 32-bit Cortex-A5 as a superior substitute for the five-year-old ARM1176JZ F -S and a major upgrade from the eight-year-old ARM926EJ-S. Fermi processors will continue to shoulder the graphics workloads in PCs, but they are taking the largest step yet toward becoming equal-partner coprocessors with CPUs. With numerous additional improvements, Fermi significantly advances diagram state of the art in this field. See MPR"The New Peripheral is Almost Here". The Coolpix S1000pj displays still photos and video clips at VGA resolution. Eventually, picoprojectors will replace bulky video projectors and will liberate portable video from the confining dimensions of tiny LCDs. First, Intel has acquired Cilk Arts and RapidMind, two small but brainy companies specializing in development tools for parallel programming. Second, Virage Logic is buying ARC International, which will alter the competitive landscape for licensable embedded-processor cores. All these moves are further evidence that forward-thinking companies are taking advantage of recessionary prices to strengthen their positions for recovery. But the new markets offer tremendous opportunities for growth, so Intel must pursue them, even at the risk of price erosion. Although Tensilica says most of the million processor cores it has shipped are performing DSP tasks already, Tensilica has always styled itself as a vendor of configurable RISC CPUs. Now, with ConnX BBE, the company is making a major play for DSPs. ConnX BBE has provisions for multicore designs and is suitable for infrastructure equipment as well as for next-generation cellphones. Only five months ago, Texas Instruments announced a 1. Now Intrinsity is unveiling a 1. Intrinsity says Hummingbird can reach 1. It could exceed that clock frequency in a faster but leakier 45nm-GP process. The official licensee is the Institute of Computing Technology ICT at the Chinese Academy of Sciences in Beijing. Although ICT is a government-owned academic and research institution, the MIPS licenses are full-fledged commercial contracts, not the limited academic licenses usually granted to universities. But among individuals, the experience varies. In tough times, wealth and health accrue even more value. Can it finally retire the ancient Dhrystone benchmark? After some quick-and-dirty testing, Microprocessor Report found CoreMark to be a major improvement. A recent Wall Street Journal article alarmed critics, but Apple has good reasons for hiring more chip designers. To create this kind of frenzy, Apple must differentiate its products from those of competitors Figure Apple revenues, Q All those little iPods add up. Despite a late and relatively slow start, the iPod soared to popularity. Some CPU architects strive to design smaller and smaller microprocessor cores, bucking the trend toward larger processors. In the Lilliputian world of microcontrollers and deeply embedded systems, smaller is definitely better. This report compares the ARM Cortex-M0, Cambridge Consultants XAP5a, Cortus APS3, and Tensilica Diamond Standard 106Micro. Meanwhile, hard-pressed programmers are tackling the job by hand. Now their task will be a little easier. CriticalBlue has introduced Prism, a code-analysis tool that helps developers diagram thread-level and system-level parallelism from legacy programs written in sequential code. After running the target program in a software simulator that captures dynamic trace data, developers can use Prism to analyze the results in numerous ways. Most important, Prism helps developers explore various what-if scenarios so they can make intelligent decisions before rewriting any code. But therein lies a paradox. Eventually, this trend will drive memory cards into obsolescence before film. TSMC will offer peripheral blocks for the SoC designs and manufacture the chips in its fabs. Make no mistake: this deal is aimed squarely at ARM. Intel wants to push the x86 architecture into smartphones and other low-power embedded systems, which ARM dominates. Anything tinier is probably an 8- or 16-bit processor. All became more famous than the products of which they are parts, says a Harvard Business School professor. These lessons and others are part of a case study that Professor Richard S. Tedlow teaches at Harvard Business School. We think the changes wrought by the are more relevant now than ever. As AMD struggles for survival, and after all known startups working on x86-compatible processors have crashed, Intel is nearer to capturing a worldwide monopoly of PC processors today than it was 23 years ago. Can everyone who handles it be trusted? My recent experience with a repair shop shows that we cannot. Our fellow In-Stat analysts are not so lucky. Unfortunately, many people believe our now collapsed bubble economy was a normal economy. As a result, they define recovery as the restoration of bubble-level business activity. This misconception is understandable for younger folks who have known nothing but bubbles. However, even some older people have forgotten what a normal-growth economy looks like. As users download this driver, the installed base of Stream-capable systems could swell to more than two million PCs. Before, users had to download and install the free ATI Stream runtime separately. All are software-development platforms for parallel processing. Starting now, Freescale is offering design services to customers that want a custom SoC. Freescale will offer intellectual property IP for the chip, will design the chip, and will manufacture the chip. The customer provides a design specification and money. At first glance, it looks as if Freescale is merely launching a design-services business, just one more design house among many. Unlike most design houses, Freescale has little interest in making SoCs entirely new from the ground up. To customize the SoC for the target application, Freescale is willing to add or remove blocks and integrate some customer-provided IP or third-party IP. It was the first time a Chinese CPU architect visited the U. Among the revelations was a startling feature: more than new instructions and other modifications that accelerate x86-to-MIPS dynamic binary translation. In other words, the Godson-3 applies hardware optimization to x86 emulation, much as Transmeta did with its Crusoe and Efficeon microprocessors. Gradually, election reformers are convincing public officials that paperless electronic voting machines are too flawed to win public confidence in the most important exercise of a democracy. Halfhill This year marked the 20th anniversary of the Hot Chips Symposium at Stanford University in Palo Alto, California, sponsored by the Call Technical Committee on Microprocessors and Microcomputers. Microprocessor Report has lightly edited the transcript of their discussion for clarity and has added comments and article references to help put some remarks into context. No longer satisfied with existing strongholds in PCs and servers, this year Intel has revived the x86 as a standalone embedded processor and has introduced the first highly integrated x86-based SoCs. And as early as next year, Intel will debut the first x86-based 3D-graphics processors. A 30-year-old CISC architecture designed for general-purpose processing would seem to be seriously handicapped against special-purpose GPUs, which are highly optimized for tasks like pixel shading and texture mapping. But Intel is undeterred. Into this colorful riot wanders Intel, casually dressed by The Gap for a come-as-you-are party. For now, they combine a PC processor core, a PC north-bridge chip, a PC south-bridge chip, and optionally a cryptography-acceleration chip. Consequently, they are relatively large and power hungry when payoff with competing SoCs. But they are also fast, highly integrated, and definitely better than a system cobbled together with three or four separate Intel chips. But would they welcome a trade that sends the hitter to Cleveland for three hitters? System designers and software developers face similar quandaries when making trade-offs with multicore processors. Even if a dual-core processor appears to be better than a single-core processor, how much better is it? Would a quad-core processor be four times better? The Embedded Microprocessor Benchmark Consortium EEMBC wants to help answer those questions. The new brand is QorIQ pronounced "Core IQ". Among the first six QorIQ devices announced is the P4080, the first eight-processor multicore chip from Freescale. Some future QorIQ chips will have at least 16 cores. In the past, programmable-logic devices were commonly viewed as prototype platforms, not as final products. FPGA developers received a big boost recently when Synplicity unveiled its ReadyIP initiative. ReadyIP allows soft-IP vendors to package their cores in a standardized format, so FPGA developers can easily integrate the IP using system-level design tools. Optionally, soft-IP vendors can protect their ReadyIP cores with encryption that still lets developers evaluate a design before purchasing a full license. One went bust, and the other was mysteriously acquired by Apple. All the enhancements make the Cortex-M3 even more suitable for microcontrollers, but fault tolerance is especially important for automotive, medical, and military applications. A full implementation of the new MIPS K Coherent Processing System with four dual-threaded cores offers the virtual equivalent of eight-way SMP. TDP is a worst-case metric, so typical workloads will draw much less wattage. Intel estimates the "average" power at mW and idle power at mW. Atom completely redefines the low-power x86 landscape. Traditional single-threaded programs essentially gain nothing by running on microprocessors with multiple cores. Indeed, the program might even run worse. Multicore processors are in vogue because the power-dissipation penalties of higher clock speeds force CPU architects to find alternatives. The newly popular alternative is to integrate multiple processor cores in a single chip, clock the cores at a lower frequency, and tell programmers to rewrite their software. The solution that seems to be emerging is explicitly coded data-level parallelism. The Core Store sells synthesizable processor- and peripheral-IP cores at fixed, published prices. With a few mouse clicks, chip developers can review online documentation, buy the IP Visa, MasterCard, and PayPal accepteddownload the files, and begin working immediately. Formally introduced inafter a year-long gestation in beta, CUDA is steadily winning customers in scientific and engineering fields. At the same time, Nvidia is redesigning and repositioning its GPUs as versatile devices suitable for much more than electronic games and 3D graphics. For Nvidia, high-performance computing is both an opportunity to sell more chips and insurance against an uncertain future for discrete GPUs. Of course, software development remains a big challenge, even provoking a recent article in The New York Times, of all places. But the discussion is equally spirited on the hardware side. One debate is about symmetric versus asymmetric multiprocessing. Should all the cores on a multicore chip be identical, or should some be specialized for different tasks? Another debate questions the value of core-level multithreading. How many threads make sense? But the company says it has no plans to resume making microprocessors. Thanks to a partnership with Synopsys, developers can license the 32-bit synthesizable processor for standard-cell implementations in ASICs as well as for FPGAs and structured ASICs. Now, anyone can license Nios II for a standard-cell design flow using industry-standard design tools, including the popular electronic-design automation EDA tools from Synopsys. In return, RapidMind claims big benefits. Some tasks run five to ten times faster, and, in some cases, performance can scale faster than the rising number of processors. On November 5, RapidMind announced Multicore Development Platform v3. Developers payoff also substitute a simpler memory-protection unit MPU or omit supervised memory management altogether. MicroBlaze v7 has other improvements as well. Xilinx has upgraded the CoreConnect interface to the latest CoreConnect Processor Local Bus PLB v4. By using this block to integrate additional peripherals, application-specific logic, or even multiple processor cores, customers can transform these off-the-shelf parts into the near equivalent of a custom ASIC. ARC licenses these subsystems to customers as soft intellectual property IP for integration in SoCs. Now, Intrinsity is playing a different role for ARM. The result is the ARM Cortex-R4X, the extreme-makeover edition of the Cortex-R4. In our July issue, we reported on another interesting collaboration between Intrinsity and AMCC. With these projects, Intrinsity appears to be successfully redefining itself as an IP provider and design shop specializing in speed-optimized embedded-processor cores. It has become clear that chip-level multiprocessing is the only visible path toward significantly higher performance, call every leading-edge processor company has a multicore strategy. The latest company to revamp its strategy is Freescale Semiconductor. The villains include hardware manufacturers, software publishers, documentation writers, mass-market retailers, and corporate downsizers. And it seems to be getting worse, not better. In addition, Titan is part of a dual-core "processor complex" that supports coherent multiprocessing. If Titan succeeds, it will admit AMCC and Intrinsity to an exclusive club formerly limited to Freescale, IBM, and P. Typically, a new market opens with highly innovative products that command high profit margins. As more companies enter the fray, competition drives prices down. Eventually, the products become so plentiful and similar to each other that they become a nearly profitless commodity. The huge V8 transformed a cute Bug into a kludgy monstrosity. Freescale Semiconductor wants to bring a similar upgrade to embedded systems, only without the kludge quotient. So this week, Freescale is unveiling the first microcontroller family with pin-compatible 8- and 32-bit devices. Microprocessor Report covered the MIPS 74K in detail shortly after its May 21 debut, but we overlooked some power-consumption estimates. I remember enjoying the same freedom to make copies of music for personal use back in the analog vinyl-and-tape days. Even in the s, when audio CDs introduced the world to digitized music, it was common to make cassette copies for the car and mix-tapes for parties. Now those features are reappearing in synthesizable embedded-processor cores. MIPS introduced the MIPS K, a new family of 32-bit synthesizable processor cores for demanding embedded applications. The preliminary results are even better than with the latest low- k solid dielectrics. Lower- k dielectrics reduce the capacitive coupling between adjacent wires, thereby improving current flow. Dozens of companies are participating as presenters or sponsors. This event will be the only Microprocessor Forum in the U. The only other scheduled forum is Microprocessor Forum Japan, on June in Tokyo. Microprocessor Forum is the longest-running independent technical conference on all aspects of microprocessors Photo A Wi-Fi network allows conference attendees to download the latest versions of technical presentations and other materials. In-Stat will also make the materials available on USB flash drives Photo The traditional Tuesday-night Expo and Demo Showcase gives attendees a chance to huddle with industry celebrities while enjoying food and drink Free link to this article: Preview: Microprocessor Forum Editorial: The Dread of Threads Multicore processors are leading the computer industry into uncharted territory. One paper is "The Problem With Threads," by Dr. Lee, chairman of electrical engineering at the University of California at Berkeley. The other paper, also authored at that university, is "The Landscape of Parallel Computing Research: A View From Berkeley," by 11 experts on microprocessor architecture. It asserts that the only path toward significantly faster CPUs is chip multiprocessing, regardless of any consequential problems with threads. NXP Semiconductor formerly Philips Semiconductors showed some fascinating preliminary results of tests with the power-consumption benchmarks that EEMBC introduced last year. Innovasic Semiconductorwhich specializes in satisfying demand for chips discontinued by other companies, wants to clone the Intel processor, which Intel recently dropped from its product catalog. Until now, only IBM has broadly licensed Power cores to chip developers. The first Freescale cores released for call are four members of the 32-bit Power e200 family. All are fully synthesizable and portable to virtually any digital IC process. Until now, with one exception, ARM has permitted licensees to synthesize ARM processors in FPGAs for development purposes only, not for product deployment. At the same time, ARM is announcing its first synthesizable processor core specially designed for FPGAs: the Cortex-M1. ARM says additional FPGA-optimized cores will follow. One award was shared by two companies, ARM and Handshake Solutions. ARM and Intel each won two awards. Some implementations use an innovative semiconductor fabrication process to bond the image sensor directly onto the parallel-processor array, creating a multilayer chip. For each award, we are publishing a brief article about the winning product or technology and the reasons for our choice. Maximum theoretical performance exceeds one trillion operations per second at 333MHz. Plenty, to anyone who can design a digital-imaging system capable of achieving such spectacular frame rates. Applications include robotic vision, intelligent video surveillance, scientific analysis of momentary events, monitoring industrial processes, interactive games, and guidance systems for unmanned vehicles and missiles. With grants from the U. Missile Defense Agency and the Office of Naval Research, scientists from Hungary, Spain, and the U. CVT combines a massively parallel processor architecture with optimized image-processing software. Some implementations use an innovative semiconductor fabrication process to bond the image sensor directly onto the parallel-processor array, creating a stacked multilayer chip. It might be amusing if anything less than our democracy were at stake. Indeed, the situation is so appalling that I suspect almost any reader of Microprocessor Report could design better hardware and software than we have now. Intel manufactured the chip in a 10-micron PMOS process on two-inch silicon wafers and furnished the device in a 16-pin ceramic dual-in-line package. To celebrate this historic chip, Microprocessor Report covered the anniversary event at the Computer History Museum in Silicon Valley, which reunited codesigners Ted Hoff and Federico Faggin. Our coverage includes transcripts of their presentations, their responses during an audience question-and-answer session, our own technical analysis of thea block diagram of the processor, our newly reconstructed instruction-set table, and an analysis of how the transformed the computer industry. The biggest improvements are error-correction codes ECC to protect caches and local memories, an optional memory-management unit MMU for both processors, and several new configuration options that can boost performance, save gates, and reduce power. The option processors are the Xtensa 7 and Xtensa LX2. And these days, it seems as if half the motorists on the road are yapping on their cellphones while driving. ARM wants to see more of its processors built into automobiles, not merely used in automobiles. So ARM has announced the Cortex-R4F specifically for the automotive market. This ignorance may seem harmless. Merely learning how to use an electronic device is challenging enough. Unfortunately, as microprocessors become ubiquitous, knowing something about them is becoming not only desirable but necessary. Intel needs immediate results. On September 26, Intel announced that quad-core server and desktop processors will begin shipping in November. Both product lines are months ahead of previously disclosed schedules. This million-transistor chip, fabricated in a modest micron CMOS process, crams proprietary 32-bit RISC processors and 585KB of SRAM onto a single compact die. Maximum theoretical performance exceeds one trillion operations per second TOPS at 333MHz. The Am is designed to replace high-end embedded processors, DSPs, and FPGAs in applications that require fast general-purpose integer and digital-signal processing. And Microprocessor Report covers new ones every year. With such abundance, it might seem daffy to use highly specialized 3D-graphics coprocessors for general-purpose number crunching. But the computational allure of GPUs is proving irresistible to the scientific community, chemical engineers, defense contractors, Wall Street financiers, and other heavy-duty math junkies. PeakStream, a Silicon Valley startup, has introduced new software and development tools that make GPUs relatively easy to program for data-intensive applications. Example A is typical sequential code without using any special function libraries. If anything, I expect Intel will be an even tougher competitor in the years to come. Surprisingly, the solutions are largely the same, too, across the design spectrum. MPF will be held on October at the Doubletree Hotel in San Jose, California. To celebrate, we are reviving the famous MPF chip portfolio every paid conference attendee gets a notebook with real microprocessor chips embedded in the coverand we have arranged a stellar lineup of presenters. Presentations will also be available on USB flash drives Photo The traditional Tuesday night expo and party is an opportunity to mingle with exhibitors and fellow attendees. The food and drinks are pretty good, too Sidebar: Microprocessor Forums in Japan and Europe The New Power Architecture Freescale and IBM Work Together and Begin Revamping PowerPC Digital years of following different paths, the two key founders of the PowerPC architecture have renewed their historic collaboration. For the first time, all the documentation will be consolidated in a common format. And hereafter, the common architecture will be called the Power Architecture. Both PC-processor giants are divesting embedded-processor businesses in the same month. Certainly, both companies need to pay more attention to their foundations. Instead of tinkering with gate arrays, designers work with a massively parallel array of preconfigured function units. Most of these units are identical ALUs or multiply-accumulate MAC units that can run autonomously. Others are register files shared by the ALUs and MACs. The first FPOA device has of these 16-bit units woven together in a tightly coupled interconnect fabric. Without those alchemists, RMI will struggle to turn lead into gold. It consists of hardware IP, software IP, and professional design services for consumer-electronics application processors. Zevio also has emulators and prototyping systems that allow customers to write software in parallel with hardware development. Zevio is compatible with several 32-bit processor cores from ARM and MIPS Technologies, as well as the ZSP family of 16-bit DSP cores. Patent and Trademark Office recently issued three new patents to Tensilica for its configurable-processor technology. They follow seven related patents issued from to In addition, the patent office has reaffirmed a key Tensilica patent issued in that was anonymously challenged a year later. As a result, Tensilica now holds an impressive portfolio of at call ten patents on configurable-processor technology. You did submit a feedback form, right? With this debut, ARM has now introduced initial members of all three of the new Cortex families announced in The Cortex-R4 duplicates the relatively high performance and relatively low power consumption of the existing ARM9, ARM10, and ARM11 families while incorporating the latest features of the ARMv7 architecture. At eight stages, the pipeline is one stage shorter than the ARM1156T2-S pipeline Figure Cortex-R4 synthesized layout. A laptop computer with information about nearly 200,000 current and former Hewlett-Packard employees was stolen from Fidelity Investments. Flash-memory drives containing secret military intelligence were pilfered from a U. Army base in Afghanistan and openly sold in street bazaars. To help with logistics, we partnered with IDG China, an offspring of International Data Group, one of the first U. As part of our China experiment, I traveled to Shanghai and Beijing to participate in our forum and meet with Chinese engineers and executives. Searing wattage compelled Intel to abandon its pursuit of high clock frequencies and instead design PC processors with power-efficient cores. And the very same immovable object persuaded IBM, Sony, and Toshiba to design the Cell Broadband Engine with a relatively simple PowerPC core surrounded by an array of power-efficient coprocessors. With Teja FP, programmers can start with existing data-plane code written in ANSI C or write new code in that language. Payoff profiling and analyzing the code, the next step is to partition the application. Each MicroBlaze core is an engine in the packet pipeline Figure A high-performance packet processor designed with Teja FP requires several MicroBlaze processor cores. This example has nine cores Figure Hardware and software development with Teja FP is highly interactive. Whereas the smallest configuration is suitable for deeply embedded microcontrollers in real-time systems, the largest configuration sets a new record for DSP benchmarks. Recent moves by ARM, Intel, MIPS Technologies, and Sun Microsystems are strengthening the competition, too. All those techniques and more are available in embedded-processor cores licensed as synthesizable intellectual property. Now MIPS Technologies is adding another option: the first licensable processor cores with hardware-enabled simultaneous multithreading. The new MIPS K family consists of four 32-bit processor cores, all related to the MIPS KE family. The key difference is pipelined multithreading. Instructions from as many as five different tasks can pass through the nine-stage pipeline of a 34K processor at the same time. ARM Ships the First Licensable, Clockless 32-Bit Microprocessor Core ARM has finally delivered the ARM996HS, the first commercially available 32-bit microprocessor core implemented in asynchronous clockless logic. If the ARM996HS succeeds, it could spark a revolution in power-efficient processing that researchers envisioned even before microprocessors were invented. But the project still has risks. Several previous attempts to introduce a clockless 32-bit microprocessor have failed, and the ARM996HS remains unproved in silicon. Their features, performance, power consumption, and prices vary according to their target applications, and they introduce some entirely new Octeon features, such as USB and voice-over-IP VoIP interfaces. We evaluated several strong candidates before picking our winner: the Cell Broadband Engine, jointly designed by the STI alliance: Sony, Toshiba, and IBM Microelectronics. We identify five broad trends in embedded processors. None of these trends actually started last year, but they gained momentum in and will be major forces in the future. The latest new microprocessor architecture to emerge is unconventional, massively parallel, and optimized for the narrow domain of high-definition digital video. Digital first commercial chip has 1,024 PEs Figure PEs are arranged in a two-dimensional array, much like other massively parallel architectures, but Connex simplified the on-chip interconnect fabric by severely limiting the connections among the PEs Figure The Connex Machine can operate on 1,024 words of data simultaneously. These 16-bit words are arranged in a single-dimensional array or vector Figure Connex created a proprietary version of ANSI C, known as Connex Programming Language CPLthat adds new vector datatypes and commands Sidebar: The Key to Massive Parallelism: Think Small The Oblique Perspective: Merry Virtual Christmas Digital Music Is Great, But I Miss Album-Cover Art! Digital music distribution allows performing artists to circumvent the obstacles of expensive recording studios, greedy record companies, and corporate chain stores. Anyone can make their music available directly to the public. Eliminating the physical media and packaging strips the music down to its essence: music. However, record-album covers were more than mere packaging. Are we sacrificing something worthwhile by distributing music as digital-audio files without visual artwork? Product differentiation and integration still matter. Hence, the rush toward alternatives to full-custom silicon, such as FPGAs, structured ASICs, and reconfigurable processors. Other TriMedia cores deliver high performance but consume too much power for the new wave of portable consumer-electronics products. The TM uses multiple techniques to cut power consumption and has new instructions and other features targeting digital video. Tensilica is preconfiguring the cores by customizing them with application-specific extensions, adding local memory and other intellectual property IPand licensing the whole synthesizable design as a drop-in module for SoCs needing video acceleration. ARC will license the SIMD extensions as parts of larger extension packages released later this year. In other revolutions, heads roll; in this one, heads talk. Into this maelstrom jumps Videantis, a startup based in Hannover, Germany. At Fall Processor ForumVideantis unveiled two synthesizable video-coprocessor modules based on the same proprietary processor core. Videantis wants to license the modules and optimized software to designers building programmable video chips for high-definition television HDTV and mobile consumer electronics. Innovative Silicon refers to positive charging as "impact ionization" and to negative charging as "hole removal. Gordon Moore and Dr. Microprocessor Report recorded and transcribed this special event. Gordon Moore Photo: Dr. That appears to be a new low price for flash-integrated ARM7 MCUs in this relatively high performance class 70MHz, 63 Dhrystone mips. All three parts are stuffed with peripherals, timers, and other accoutrements of general-purpose MCUs. In addition, Philips has included features to address the shortcomings of previous 32-bit MCUs and to duplicate some advantages of 8- and 16-bit devices. The only differences among the LPC2101, LPC2102, and LPC are their amounts of internal flash memory 8KB, 16KB, or 32KB and SRAM 2KB, 4KB, or 8KB Table Power-saving modes in the new LPC2101, LPC2102, and LPC Table Feature comparison of the new Philips LPC2101, LPC2102, and LPC2103; the Atmel AT91SAM7S32; and the Oki Semiconductor ML67Q406x and ML67Q500x Preview: Fall Processor Forum Multicore Processing Dominates 18th Annual Conference Not since the days when RISC and VLIW challenged the CISC orthodoxy has there been such an upheaval in microprocessor design. Microprocessor Report has provided front-line coverage of the multicore revolution since its payoff in the s. The theme of Fall Processor Forumour 18th annual fall conference, will be "The Road to Multicore. Cavium gained fame with its award-winning Nitrox security coprocessors in and soon will begin shipping its Octeon NSP multicore network processors with integrated security engines. In addition, Cavium can freely export Octeon EXP chips to countries subject to U. Patent Covers Automated Tools for Customizing Processor Cores With Rich Belgard A showdown may be looming between ARC International and archrival Tensilica over who invented the software tools and methods for customizing synthesizable microprocessor cores. Both companies have won important U. Whether or not ARC and Tensilica come to legal blows, their growing option portfolios should worry other companies working in the expanding field of configurable processors. In general, Microprocessor Report agrees with ARC that U. However, the complex language and convoluted history of the patent defy easy analysis and interpretation. It explicitly promotes TIE as a higher-level alternative to standard design languages like Verilog and VHDL Actel Mixes Signals on FPGAs Programmable Chips Will Integrate Analog, Digital, and Memory As design costs soar like housing prices, ASIC alternatives are multiplying like Realtors. Actel has announced a technology called Fusion that, for the first time, can integrate mixed-signal logic with an embedded-processor core, flash memory, and SRAM in the same programmable-logic device. With Fusion, a single FPGA could perform some or all of the analog- and digital-processing functions in an embedded system. Fusion will integrate hard-wired analog peripherals with hard and soft intellectual-property IP cores in an FPGA. A soft embedded-processor core is optional. Intended for low-cost desktop computers, servers, and embedded systems, these and 64-bit chips are rapidly becoming as sophisticated as any designs in the world, falling short in performance only because Chinese fabrication technology lags behind the rest of the industry by two process generations. Weiwu described the Godson-1 and Godson-2 in unprecedented detail and revealed some of his ambitions for the Godson-3. After analyzing this information, MPR believes the Chinese already are capable of designing world-class microprocessors, if they can gain access to world-class fabrication technology. Today, Java is successfully running on millions of cellphones and other embedded systems. Now, ARM is taking up another challenge: reducing code bloat when compiling Java bytecode with just-in-time JIT compilers or static native compilers. Some specially customized versions of configurable processor cores have achieved higher EEMBC scores in simulation. As newly certified EEMBC scores show, the 1. Using feedback from early adopters of its massively parallel configurable-processor core, Elixent has introduced D-Fabrix v2. The original Chess architecture that inspired D-Fabrix lacked these muxes Figure Benchmark tests comparing the simulated performance of a D-Fabrix v2. But with instruction words stretching as long as bits, this architecture does seem almost unbelievable. Last month, at Spring Processor ForumSilicon Hive introduced two new ULIW processor cores, the Avispa-IM1 and Avispa-CH1. This time, the company is targeting pixel processing as well as wireless communications. Microprocessor Report has added a sidebar analyzing the new MIPS KE processor family. The 24KE adds DSP extensions to the high-performance 24K family of synthesizable embedded-processor cores. Halfhill Table: Feature comparison of the MIPS 24KEc, 24KEf, 24KEc Pro, 24KEf Pro, 24Kc, diagram, 24Kc Pro, and 24Kf Pro embedded-processor cores Float Without Bloat ARC Adds Economical Floating Point to Customizable Processor Cores For years, ARC International has considered adding an optional floating-point unit FPU to its 32-bit customizable processor cores, but it has always been deterred by the cost of the additional logic gates and power. A fully equipped FPU with its own pipeline and register file could double or triple the silicon area of a small embedded RISC processor. These companies are the Hatfields and McCoys of the semiconductor industry. Altera fired the last shot by introducing Nios II at Embedded Processor Forum This week at Spring Processor Forum, Xilinx is blazing back with MicroBlaze v4. The finished RAID controller chip is now solving space problems of a different sort by bringing affordable network-attached storage NAS to home and small-business users. The new LEON-derived chip is the IT network storage processor from Infrant Technologies, a four-year-old privately held company in Fremont, California. This is the second RAID controller Infrant has designed using parts of LEON1, a 32-bit processor core adhering to the SPARC V8 instruction-set architecture. The European Space Agency freely distributes a synthesizable VHDL model of LEON1 under a GNU license. Innovation is running wild in the embedded industry, and SPF will be a showcase for radical multicore designs, aggressive new DSPs, new embedded-processor architectures, and much more. All these milestones provide more reasons to upgrade from 8- or 16-bit MCUs to 32-bit ARM-based devices. Is it an MCU or an SoC? The new chips belong to the PowerQUICC II Pro series and are called the MPC8360E and MPC8358E. The "new" 32-bit synthesizable processors are actually preconfigured cores, optimized for embedded applications in the low-power and high-performance realms. Although chip designers can further customize the cores for specific applications, the ready-made configurations are intended to accelerate design projects and allow easier comparisons with competing processors. The six preconfigured cores are the ARC 605, 610D, 625D, 710D, 725D, and 750D. All but one the have DSP extensions. Patent EEMBC Expands Benchmarks New Digital Entertainment Suite Tests Audio, Video, Cryptography After two years of labor, the Embedded Microprocessor Benchmark Consortium EEMBC has delivered its largest new test suite since introducing its original benchmarks in Indeed, the new Digital Entertainment suite DENbench has more tests than all five suites of the EEMBC benchmarks put together. In all, there are 69 new tests, though most are alternative datasets for a smaller number of basic tests. They are grouped into four smaller suites that are useful for a broad range of applications, from consumer electronics to secure communications and digital rights management DRM. More recently, the company has been introducing communications processors with security engines, a subtle but strategic shift. By integrating both communications and security, a single chip can do the job of two. Before long, security acceleration will be as common as caches in all types of microprocessors. Server processors have the fattest caches. But unsung embedded processors are at the forefront of microprocessor evolution. While the PC market is agog at dual-core 64-bit processors, the embedded market already takes such chips for granted and will deliver processors with four, eight, and sixteen 64-bit cores this year. Only the need for power efficiency restrains embedded chips from matching the high clock frequencies of PC processors and the bloated transistor budgets of the biggest server processors. Another company announced a mind-numbing barrage of new products and spent nearly a billion dollars on a binge of acquisitions. And the biggest competitor announced plans to greatly expand its licensing strategy. Tantalizing details will trickle out in February, when IBM presents several papers about Cell at the International Solid-State Circuits Conference ISSCC in San Francisco. Until then, nothing beats a weighty 57-page patent issued to IBM, Sony, and Toshiba by the U. Patent and Trademark Office on October 29, Patent 6,809,734 describes the Cell architecture in detail, with 42 pages of illustrations. Google finds 223,000 hits for the term on the Internet, remarkable for something as arcane as semiconductor chip manufacturing. Not since a falling apple led Sir Isaac Newton to discover universal gravitation have so many people been so captivated by a scientific law. Now, ARM and Handshake Solutions a line of business within Royal Philips Electronics in the Netherlands think conditions are changing in favor of asynchronous logic. Handshake Solutions has been working closely with ARM to design a fully asynchronous ARM9 processor core that ARM will license commercially in 1Q05. It will be the first commercial asynchronous 32-bit microprocessor. Four of the six presentations in the high-performance embedded session at Fall Processor Forum FPF described impressive new multicore designs. One new product family integrates up digital 16 cores on a single chip. Clock speeds are soaring to 1. Although some other embedded applications require high-performance processors, the growing demands call packet routing, control-plane processing, and wireless infrastructures are forcing chip vendors to push their designs farther than ever before. Dual-core x86 processors for PCs and servers are coming soon from AMD and Intel, along with their transition to the x architecture. Meanwhile, high-performance embedded processors and digital signal processors DSP are evolving at an even faster rate. Networking chips with as many as 16 processor cores are making their debut, along with massively parallel processors that squeeze hundreds of cores onto a single chip. All that and more is happening at Fall Processor Forum FPFformerly known as Microprocessor Forum. FPF will be held October at the Fairmont Hotel in San Jose, California. Among other things, it erases all doubt that ARM is becoming a start-to-finish provider of semiconductor intellectual property, not just a vendor of embedded microprocessor cores. So it goes with the LAHF and SAHF instructions, which AMD originally dropped from the 64-bit AMD64 architecture, then restored after discovering some software still needs them. See MPR"A Tale of Two Instructions". We reported that Intel first introduced LAHF and SAHF in the 16-bit processor ofmainly to speed up context switching for operating systems. So imagine our surprise when a sharp-eyed reader from Germany took issue with our version of the historical record. Maybe it was something trivial, like a Pet Rock. Maybe it was something important, like a Pete Rose rookie card. Or maybe it was something both trivial and important, like the SAHF and LAHF instructions in the x86 microprocessor architecture. The strange story of the death and resurrection of these instructions is a classic example of the reason the x86 architecture has grown so complex over the past 26 years. Answer: outsourcing it to a robot. However, they are also suitable for structured ASICs and regular SoCs, especially as a migration path from FPGAs if production volumes climb. No wonder ARC International wanted to delay revealing everything about its new ARC processor core until a marketing plan was in place. For SoC developers, Xtensa LX preserves the advantages of a customizable CPU architecture while laying the groundwork for future development tools that will further automate the task of creating an optimized SoC design. Business and residential customers eager for lower-cost alternatives are eyeing voice-over-Internet-Protocol VoIP telephony, which piggybacks digitized voice packets onto existing Internet services. Two of the chips have Ethernet media-access controllers, and all have time-division multiplexers TDMDDR memory controllers, 32-channel DMA, and generous amounts of on-chip SRAM. In all, there are eight new PowerQuicc chips. The most significant improvements over existing PowerQuicc processors are higher-performance CPU cores, faster memory systems, enhanced network interfaces, and integrated security engines for encrypting and decrypting data packets. However, the much publicized "Power Everywhere" initiative still falls short of matching the flexible licensing models and customizing options from competing IP vendors. Almost all these presentations will be the first technical disclosures of their products. The new processors run the gamut from traditional RISC and CISC architectures to bold new designs optimized for communications, mobile multimedia, machine vision, and signal processing. The new Au supports Internet Protocol security IPsec and the Secure Sockets Layer SSL protocol for virtual private networks VPN. We compared all the new instructions, modified instructions, deleted instructions, and modifications to the register files. We also compared the memory-addressing schemes and many other architectural features, such as data-addressing modes, context-switching behavior, interrupt handling, and support for existing and 32-bit x86 execution modes. In every case, we found that Intel has patterned its 64-bit x86 architecture after AMD64 in almost every detail. However, we also found a few differences that could make some software written for one 64-bit architecture incompatible with the other architecture. The Xilinx deal is final, averting a further bidding war or the intercession of other suitors. The new er ARC processor is fully compatible with its still-available predecessor and is intended for customers willing to tolerate a larger core in return for higher performance. Although massively parallel processors are becoming almost commonplace, the X10q steps forward with a massively pipelined architecture. This unusual approach is justified for a high-performance packet processor that performs repetitive tasks in serial fashion. The massively parallel chip is hitting all call design targets for clock frequency MHzpower consumption less than 2Wand peak floating-point performance GFLOPS. Last fall, TI licensed additional Sonics technology for its OMAP wireless-communication processors, and an industry-standards body adopted the core-interface protocol backed by Sonics. In a bid to regain the initiative, ARC has extensively revamped its product line. ARC has also decided to offer preconfigured CPU cores for vertical applications, and the first example is an ARC with new hardware extensions and software codecs designed for portable digital-audio products. The latest example is a configurable parallel-processing architecture from Silicon Hive, a Netherlands-based startup funded by Philips Electronics. Instead, the TM will spawn a new generation of standard-part Nexperia media processors designed and manufactured by Philips. Motorola says the enhancements will eventually appear in a future architecture from StarCore LLC, a spinoff formed last year by Motorola, Infineon, and Agere formerly Lucent. If you want a big MAC, see PicoChip Design. Known as the HiFi Audio Engine, the optional extensions include 54 new instructions that accelerate common algorithms for digital-audio encoding and decoding. The package, called ARCprotect, includes new instructions, registers, and middleware as licensable intellectual property IP for the current ARCtangent-A5 and future ARC microprocessor cores. The new A7V05 family initially has four members, all with ARM7TDMI processor cores running as fast as 70MHz. Nothing validates a trend like the migration of technobabble to everyday language. To make designing secure embedded systems easier, ARM is adding new security extensions to the ARMv6 architecture. The new TrustZone extensions are relatively simple, consisting primarily of one new instruction, a new configuration bit, and an additional permission level that supplements the existing user and privileged modes. The goal: a more flexible system-on-chip SoC processor that consumes less power and adapts quickly to different tasks, amortizing the development costs of an SoC over multiple projects. No wonder everyone is looking for ways to exorcise the demon. Designed primarily for wireless infrastructures, the MRC is an off-the-shelf alternative to a costly ASIC project or a conventional DSP. Custom extensions can include new instructions, registers, and function units. In minutes, the tool can evaluate thousands of possible extensions and sort them by performance clock cycles and efficiency gate count. Two thrusts of the so-called Radio Free Intel initiative are a new microprocessor architecture and better radio integration with mainstream fabrication technology. The first goal is to create multiband communications processors that can automatically reconfigure themselves on the fly for different wireless standards. Fisher is winning the award for his pioneering work on VLIW. Patent and Trademark Office to reexamine one of the patents on configurable development tools issued last year to Tensilica. Embedded-systems developers keep using these puny chips because they are unbeatably cheap, sip miniscule amounts of power, and are small enough to add a dab of silicon intelligence to almost anything large enough to see. Hoping to displace 8- and 16-bit chips with more-powerful and more-profitable devices, Philips Semiconductors is introducing a new line of ARM7-based 32-bit MCUs. To sweeten the bait, Philips is fabricating the new MCUs in a special micron CMOS process that offers the option of embedded flash memory. The "new" embedded processor is the Pentium M, formerly known as Banias, which Intel introduced in March as part of the Centrino mobile PC platform. Ubicom meaning "ubiquitous communications" is a company that definitely thinks small when it designs packet processors for wired and wireless systems. Ubicom designed the IP for wireless access points, wireless LAN WLAN bridges, broadband modems, home routers, and other consumer or enterprise products that operate near the edge of a network. Javalon-1 is the first member of a small family of cores that will have minor variations on the same basic design. Chip designers can use Javalon-1 as the basis for a self-sufficient microcontroller or as a slave to another microprocessor core on an SoC or ASIC. At Embedded Processor ForumMIPS introduced the M4K Pro synthesizable processor core, which allows customers to add application-specific instructions. More recently, MIPS announced that all soft processors in the Pro Series are user extendable, thanks to a technology MIPS refers to as CorExtend. Initial Pro Series cores, in addition to the M4K, are the 4KSd, 4KEp, 4KEm, and 4KEc. This article analyzes CorExtend and compares it with the configurable-processor technology from ARC International and Tensilica. The company has announced a new line of Crusoe SE Special Embedded processors aimed at embedded systems that need to run x86 software with high performance and relatively low power consumption. If archcompetitor ARC International is granted U. Bob Rau, Hewlett-Packard Fellow, pioneer of VLIW architectures, and recipient of numerous awards, died of cancer at his home in Los Altos, California, on December He was Before joining HP inRau cofounded Cydrome in and was chief architect of the Cydra-5 computer, one of the first VLIW systems. Their open-ended multiyear agreement includes joint technology development and shared fab capacity. The Beijing-based startup, BLX IC Design Corp. The C5XL appears to achieve the impossible: it adds a deeper pipeline, Intel-compatible SSE extensions, a faster FPU, support for two-way multiprocessing, a more-efficient L2 cache, and other improvements while actually shrinking its size in the same fabrication process. The new chip is based on the 405D4 embedded processor core, an evolution of the 405B3 core introduced with the first chip in this series, the 405GP. But by trimming down the awesome 64-bit Power4 server processor and adding AltiVec diagram extensions, IBM has created an impressive and affordable PowerPC chip for smaller servers, graphics workstations, and desktop computers. The bridge allows system-on-chip SoC developers to integrate CoreConnect-compatible intellectual property IP with Xtensa processor cores. AMD quickly followed a week later by announcing two faster speed grades of the mobile Athlon XP: the andwhich run at GHz and 1. They are shipping in notebook computers from Compaq and Fujitsu. These days, TI rarely spells out OMAP, which stands for Open Multimedia Applications Platform. The new OMAP chip unites a slightly modified ARM9TDMI microprocessor core with a TMS320C55x DSP core plus a generous amount of on-chip memory and a host of useful peripherals. TI is offering the OMAP for embedded applications that need real-time control processing and data-intensive signal processing. Actual core frequencies of the new Athlon XP processors are GHz and 2. The new top-of-the-line 2. The other three new processors run at, and 2. All four processors have the same Northwood core as other recent Pentium 4 chips. But LinkUp says the USB interface and souped-up UARTs on the L can nibble a few dollars off the cost of a typical Bluetooth implementation. Now Imsys is introducing an enhanced version of its GP processor known as the Cjip. The most interesting new feature is that Imsys has developed an entirely new instruction set to supplement the Java instruction set, which has also been improved. Yet IBM has successfully created a similar option by crossing a fast PowerPC core with the luxury features of a highly integrated communications chip. The result is the PowerPC 440GP, which IBM disclosed last month at Embedded Processor Forum. The 440GP is the first chip to use the PowerPC embedded-processor core and is the first implementation of Book E, the embedded PowerPC architecture defined by IBM and Motorola. The new PowerQUICC II MPC is designed for midsize routers, switches, access concentrators, wireless base stations, and other communications equipment. NetVortex is the first licensable microprocessor architecture designed for packet processing. Some of these systems will use a new version of Crusoe that has twice as much on-chip L2 cache. Transmeta has also revealed a two-year roadmap of processors with higher clock speeds, greater integration, lower power consumption, and new VLIW cores. The is intended for low-cost network equipment, such as small-office routers, LAN switches, and home DSL gateways. Now ARC Cores is taking the next step: CPU "plug-ins. Three of the new embedded processors are Pentium III designs, and two are Celeron designs. Sitera recently began sampling a multiprocessor chip called the Prism IQ and plans to start production in 4Q00. As with similar NPUs from C-Port, IBM, and Intel, the IQ is intended to replace some of the dedicated ASICs found in routers, switches, and network-gateway devices. And the is almost pin compatible with therequiring only a lower Vcc supply V and different clock inputs for its core, so developers can make boards that work with either chip. Lexra says the LX is better suited for next-generation micron fabrication processes. NEC also benchmarked its V a 32-bit CPU based on a proprietary architectureand Toshiba tested its TMP95FY64F a proprietary 16-bit microcontroller. To put the results in perspective, MDR has derived its own unofficial "EEMBCmark" composite scores. Indeed, the cores are apparently too compatible for ARM, which has filed a patent-infringement lawsuit against picoTurbo in U. District Court in San Jose. QED will soon follow with the RM7000B, which uses micron transistors on the same-size die, boosting clock frequencies to 500MHz. The deal gives customers the option of paying a design-use fee instead of the higher cost of a MIPS architectural license while saving the time and trouble of porting a soft core to an IC process themselves. The Texas Instruments TMS320C62x-series DSP core, already the T. Rex of digital-signal processing, is about to be surpassed by an even more powerful beast. The result is the new SH7615, which samples in March and is scheduled for volume production in June. It also looks forward to the likely trends inpredicting which companies, processors, and product categories will generate the most news in the coming year. The technology allows developers to rapidly create application-specific VLIW processors with compatible development tools, simulators, and RTOS kernels. The Fremont-based company plans to integrate the 4Kp with its own DSP core to create a system-on-a-chip SOC device for wired-communications products. Analog Devices ADI and StarCore claim their C compilers can achieve a significant amount of the performance normally associated with hand-coded assembly language. Cirrus is aiming Maverick at next-generation products that can download and play audio files from the Internet, in addition to performing the more common tasks expected of handheld computers. It achieves some other firsts as well. It joins a growing line of synthesizable embedded cores from Mips, including the MIPS32 4Kc, 4Kp, and 4Km. The 4Km combines features of the 4Kc and 4Kp cores, which were announced in May Table Feature comparison of the MIPS32 4Kc, 4Kp, and 4Km cores Intel Network Processor Targets Routers IXP Integrates Seven Cores for Multithreading Packet Routing Only Intel option have this kind of luck: it gets sued by Digital Semiconductor for patent infringement, ends up acquiring its foe after an out-of-court settlement, gains a billion-dollar fab and a StrongArm license in the deal, and then discovers that it has also inherited a groundbreaking network processor that was secretly under development. Perhaps Intel should encourage competitors to file lawsuits more often. Is it embedded-memory logic or embedded-logic memory? It has very long instruction words VLIWmultimedia instructions, digital-signal-processing DSP features, a customer-extensible instruction set, and configurable cores. And the cores are designed to be combined with macro libraries to build system-on-a-chip SOC parts for consumer electronics, automotive-navigation computers, and communications devices. The new LX is expected to deliver Dhrystone MIPS at a worst-case clock frequency of MHz. One of the latest companies to swell the tide is SandCraft, which is introducing a new MIPS-compatible embedded CPU core with digital-signal-processing DSP and single-instruction, multiple-data SIMD extensions. EEMBC has been working on its benchmarking methods for almost three years. The new architectures, known as MIPS32 and MIPS64, are and 64-bit derivatives of existing MIPS architectures. The company also announced the first two cores based on MIPS32: the 4Kc and the 4Kp, popularly known as Jade and Jade Lite. Jawa now offers numerous enhancements over earlier versions, including more efficient garbage collection, scrap collection, tighter security bolts, and vital bug fixes for the dynamic compiler.
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Balls are paid for and provided to Minor League clubs by their parent affiliates.
Students were given an excerpt from a Theodore Roosevelt speech to justify the Roosevelt Corrolary.
After two centuries of careful, detailed regulation, the tea trade was suddenly exposed to the cut-and-thrust of international competition in which English, American and Dutch buyers frantically bid against each other for a supply which was far below the demand.
Likewise, the Systems Engineering program provides broad knowledge of the approaches for managing large-scale engineering systems as well as effectively designing these systems.